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PCB Layout Engineer, Intelligence Systems

Anduril - Reston, VA, United States - In-office - posted 2026-08-14

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Salary: USD 86,000 - 0 / annual

Anduril Industries is seeking a PCB Layout Engineer to join the Intelligence Systems team in Reston, Virginia. This role focuses on full-cycle PCB design for advanced defense and intelligence community applications, including requirements gathering, schematic design, component selection, layout execution, bring-up, testing, debugging, and system integration. Key responsibilities include: - Collaborating with engineers to produce high-reliability, highly manufacturable printed circuit board designs - Applying modern design standards and guidelines across high-speed digital, precision analog, RF, and high-power implementations - Establishing and refining internal design for manufacturing (DFM), design for assembly (DFA), and quality standards - Developing and maintaining PCB design processes, component libraries, and database standards - Coordinating external PCB design resources during design surges - Managing multiple concurrent projects in a fast-paced environment - Communicating effectively with fabrication partners to ensure boards meet specifications Required qualifications include an Associate's degree in electrical engineering or equivalent with 0-2+ years of professional PCB layout experience. Candidates must demonstrate expertise in IPC standards (CID/CID+ certification), PCB fabrication processes, and Altium Designer CAD tools. Experience is required with diverse board types including high-density, high-layer-count digital designs (>16 layers), power electronics, flex circuits, RF circuits, HDI, and thick boards (>1.6mm). Knowledge of signal and power integrity principles, high-speed digital interfaces (USB, PCIe, Ethernet), and controlled impedance routing is essential. Eligibility to obtain and maintain a U.S. Secret security clearance is required. Preferred qualifications include experience with dense high-pin-count packages (FPGA fanout), high-speed SERDES and DDR memory design, SoC FPGAs, alternative ECAD tools (Siemens Xpedition, Cadence Allegro), sequential lamination structures, and air-gapped network environments.

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