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RadixArk is seeking a Member of Technical Staff to optimize the lowest layers of the AI infrastructure stack—kernels, runtimes, compilers, and communication libraries—to unlock maximum efficiency from modern accelerators and interconnects. This role is critical to scaling training and inference across thousands of GPUs, where microseconds and memory bandwidth matter. Your work will directly shape the performance envelope of next-generation AI systems.
You will design and implement high-performance kernels for AI workloads, optimize compiler and runtime stacks for ML systems, and improve distributed communication efficiency across large GPU clusters. This is a deeply technical role for engineers who enjoy working close to hardware and solving performance problems at scale.
Required qualifications include 5+ years of experience in systems, compiler, or performance engineering; strong expertise in CUDA or accelerator programming; deep understanding of GPU architecture and memory hierarchy; experience writing or optimizing high-performance kernels; strong background in compilers, runtimes, or code generation; experience with distributed communication libraries (NCCL, MPI, RCCL); solid knowledge of networking and interconnect technologies; proficiency in C++ and Python; and strong debugging and profiling skills at system level.
Strong plus qualifications include experience with Triton, TVM, XLA, or MLIR; experience building compiler passes or IR transformations; familiarity with NVLink, InfiniBand, or RDMA; experience optimizing collective communication at scale; background in HPC or performance-critical systems; contributions to kernel/compiler/ML systems open source; experience scaling workloads to 1000+ GPUs; and experience with mixed-precision or quantized kernels.
