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Normal Computing is building novel silicon that leverages thermal noise as a computational resource, enabling 10-100× more AI inference per dollar and watt compared to conventional chips. The company co-designs a full stack including AI-native EDA systems and advanced ASICs, backed by $85M+ from leading deep-tech investors.
As an RTL and Physical Design Engineer, you will own the complete design flow from microarchitecture through tapeout. This role bridges classical ASIC design with novel computing architectures in an environment where hardware and algorithms are developed in parallel.
Key responsibilities include:
- Writing and owning synthesizable RTL in SystemVerilog for datapath logic, control, and memory interfaces
- Translating high-level architecture specifications into implementable microarchitectures
- Collaborating with verification teams on verification plans, debug, and coverage closure
- Managing the full backend design flow: floorplanning, place and route, clock tree synthesis, DFT insertion, timing closure, and LVS/DRC
- Participating in design reviews and contributing to architecture decisions
- Creating tapeout checklists and supporting post-silicon characterization
Ideal candidates have hands-on production RTL experience in SystemVerilog, at least three silicon tapeouts across any node or company size, and experience with datapaths and pipelines where microarchitecture was not fully pre-specified. Strong debugging skills across simulation, waveforms, and formal methods are essential. You should be comfortable working directly with architects, design verification engineers, and fab representatives in an environment where specifications evolve in parallel with design.
Bonus experience includes work at AI chip companies with tightly coupled design/verification/PD workflows, familiarity with RISC-V or open ISAs, and exposure to AI-assisted RTL or EDA tooling.
