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Normal Computing is building custom silicon that leverages thermal noise as a computational resource, achieving 10-100× better AI inference efficiency per dollar and watt compared to conventional chips. The company co-designs a full stack including AI-native EDA systems and advanced ASICs, backed by $85M+ from leading deep-tech investors.
As Hardware Engineer, Architect, you will define the silicon and system microarchitecture for Normal's unconventional compute platform, driving architectural trade-offs that unlock 100–1000x energy efficiency gains over traditional digital chips for LLM and diffusion model inference. You will lead hardware/software co-design efforts to break the von Neumann memory wall by translating transformer architectures (KV-cache management, attention mechanisms) and diffusion execution flows into custom mixed-signal compute tiles, memory hierarchies, and tile interconnects.
Key responsibilities include:
- Compute Architecture: Define the architecture and microarchitecture of novel AI accelerator compute blocks, including PE array design, datapath organization, and efficiency techniques like sparsity exploitation and reduced-precision computation.
- Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications, identifying where architectural innovation creates the most leverage and producing unambiguous microarchitecture documents for RTL engineers.
- Full-Stack PPA Tradeoffs: Reason across algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints to defend performance, power, and area trade-offs.
- ISA Co-Design: Partner with the compiler lead on instruction set architecture co-design, ensuring the programming model and microarchitecture meet in the middle.
- Prototyping Strategy: Direct block-level pre-silicon validation, decide which microarchitecture questions need answering, and partner with FPGA Design Engineers to de-risk decisions before tapeout.
- Research Fluency: Stay current with AI accelerator research and articulate where Normal's approach differs from existing solutions.
Required qualifications: degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. Substantial experience in architecture or microarchitecture of high-performance digital systems (AI accelerators, compute engines). Fluency translating between algorithm-level analysis and hardware specification. Experience with simulation-driven architecture and cycle-accurate modeling. Familiarity with quantization and reduced-precision approaches. Experience writing microarchitecture specifications and working with RTL engineers. Proficiency in Python or C++ for performance modeling and SystemVerilog or equivalent RTL. Comfort operating in environments where architecture is actively being discovered.
