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Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. We are seeking an experienced Principal/Manager for Foundry Partnership & ASIC Program Management to lead strategic foundry engagements and end-to-end execution for advanced-node ASIC projects, with a target tapeout in Q4 2027.
You will serve as the primary liaison between our engineering team and foundry partners (specifically Samsung Foundry), owning the commercial, technical, and operational lifecycle from contract execution through tapeout delivery.
KEY RESPONSIBILITIES:
Foundry Partnership & Tape-out Management:
- Drive strategic relationships, NDAs, MSAs, and Foundry Access Agreements with Samsung Foundry and its ecosystem partners (IP vendors, EDA tool providers, OSATs)
- Act as primary point of contact for the Foundry's Customer Engineering and business development teams; lead regular business/technical reviews
- Evaluate MPW runs vs. dedicated full-mask schedules to optimize cost, lead times, and risk profile
ASIC Technical Program Management:
- Own the tapeout lifecycle from RTL freeze, synthesis, and P&R through final DRC/LVS sign-off and GDSII submission
- Align internal design teams (RTL, Architecture, DV, Physical Design) with external foundry support to address technical blockers proactively
- Establish contingency strategies for schedule deviations, design modifications, or IP integration delays to meet the 2027 deadline
Quality Assurance & Reliability:
- Establish silicon validation, ESD, and Latch-up testing criteria aligned with foundry guidelines
- Oversee process monitor data, Wafer Acceptance Testing (WAT), yield metrics, and defect density tracking during silicon fabrication
- Partner with OSAT vendors to manage package substrate development, assembly, and post-silicon bring-up readiness
REQUIREMENTS:
- 8+ years in the semiconductor industry, with at least 3–4+ years directly in Foundry Relationship Management, ASIC Technical Program Management, or Physical Design Implementation
- Proven hands-on track record delivering tapeouts in sub-8nm advanced process nodes; direct experience with Samsung Foundry ecosystems and tapeout flows strongly preferred
- Solid understanding of PDKs, design rules, third-party IP licensing (PCIe, CXL, LPDDR, SerDes, etc.), and EDA sign-off flows (DRC/LVS/STA)
- Strong negotiation skills and fluency in both English and Korean to communicate effectively with internal leadership and external foundry stakeholders
