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Ambiq is seeking a Director of Physical Design to lead and scale the physical implementation organization for next-generation ultra-low-power microcontroller (MCU) products. This is a strategic leadership role responsible for driving the physical design roadmap, ensuring world-class PPA (power, performance, area), and delivering robust silicon for high-volume embedded applications.
You will guide a multidisciplinary team across physical implementation, methodology, and signoff, partnering closely with architecture, RTL design, analog/mixed-signal, verification, and product engineering to bring innovative MCU solutions to market.
Key responsibilities include defining and executing physical design strategy for low-power MCU product lines; building, mentoring, and leading a high-performing global physical design team; establishing best-in-class methodologies for low-power, high-reliability physical implementation; and driving continuous improvement in design flows, automation, and signoff quality.
You will oversee full-chip and block-level physical design including floorplanning, power planning and low-power architecture implementation, clock tree synthesis, place & route, timing closure, physical verification (DRC/LVS), and EM/IR reliability signoff. You will ensure optimal PPA tradeoffs tailored for ultra-low-power MCU architectures.
Cross-functional collaboration is critical: partnering with architecture and RTL teams to influence early design decisions, working closely with analog/mixed-signal teams to integrate mixed-signal IP into SoCs, collaborating with product engineering and operations to ensure manufacturability and yield, and interfacing with foundries on technology capabilities and design rules.
You will own physical design schedules, resource planning, and risk management, ensure first-silicon success through rigorous signoff and validation processes, and drive tape-out readiness and post-silicon debug support.
Required qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field; 15+ years of experience in physical design for complex SoCs with at least 5 years in leadership roles; proven track record of delivering multiple chips to production; deep expertise in low-power design techniques (multi-Vt, power gating, DVFS, retention), physical design tools (Synopsys, Cadence, Mentor), and advanced process nodes (40nm and below); strong understanding of MCU architectures and embedded system constraints; excellent communication, leadership, and cross-functional collaboration skills.
Preferred qualifications include experience with mixed-signal SoCs and analog IP integration, background in high-volume consumer or industrial MCU products, and familiarity with security considerations in embedded systems.
