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Graphcore is building next-generation AI compute infrastructure as part of the SoftBank Group. The company develops the complete AI compute stack—from silicon and software to datacenter-scale infrastructure—and is expanding its engineering teams globally.
This role is for an experienced Design for Testability (DFT) Engineer to join the Silicon team in Bristol or Cambridge. You will work on next-generation AI chip designs targeted at data center applications, collaborating closely with design, verification, physical design, and product engineering teams.
Key responsibilities include:
- Developing and implementing DFT strategies and methodologies for advanced semiconductor designs
- Integrating DFT requirements into the overall design process across multiple teams
- Keeping current with industry trends in DFT and adopting the latest techniques
- Ensuring production test quality and manufacturability of AI accelerator chips
- Working with RTL design, simulation, debugging, synthesis, and static timing analysis (STA)
You should have strong technical expertise in DFT methodologies, hands-on experience with RTL design, simulation, synthesis, and STA, and a demonstrated focus on quality and production test considerations. A self-motivated work ethic and ability to collaborate across engineering disciplines is essential. This is an opportunity to shape the future of AI infrastructure at a well-funded, fast-growing company backed by significant long-term investment.
