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Salary: USD 131,000 - 243,000 / annual
Neuralink is seeking a Design Verification Engineer to join the System-on-Chip (SoC) team within the Implant division. The role focuses on ASIC design verification for brain-computer interface devices that restore movement to the paralyzed and sight to the blind. You will work on high-throughput, low-power digital signal processing (DSP) modules, collaborating with a team of exceptional engineers pushing the frontiers of neurotechnology.
Key responsibilities include developing and executing comprehensive verification strategies for complex digital systems, writing and maintaining SystemVerilog testbenches, building automation flows using Python, Perl, Tcl, and shell scripting, and establishing code coverage and regression testing frameworks. You will participate in all phases of the design cycle—from architecture and microarchitecture through RTL, verification, and physical design—using industry-standard tools.
Required qualifications: minimum 3 years of digital ASIC verification experience, strong SystemVerilog expertise, and proficiency in automation scripting languages. You should have hands-on experience with code coverage metrics and regression test setup.
Preferred qualifications include formal verification experience, UVM methodology knowledge, SystemC/C++ modeling, IEEE-1801 (UPF) power-aware simulation flows, low-power gate-level simulation, FPGA/emulation experience, ARM/RISC-V processor knowledge, AMBA bus familiarity, and lab system bring-up and debugging skills. Experience with complex SoC testbench development and power-aware verification is highly valued.
This is a full-time position offering competitive base salary ($131,000–$243,000 USD), RSU equity, comprehensive health insurance, paid time off, commuter benefits, and meals. The role offers rare opportunity to impact cutting-edge brain-computer interface technology.
