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Salary: USD 200,000 - 300,000 / annual
Positron AI is building next-generation AI inference accelerators designed for low-latency, high-throughput large language model inference. The company's first custom ASIC, Asimov, delivers several times more tokens per dollar and tokens per watt than leading GPUs at a fraction of the power. In September 2026, Positron raised $875 million at a $5 billion valuation led by NEA.
As Senior DFT Engineer, you will own Design for Test implementation end-to-end: defining the DFT micro-architecture for accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with backend design partners, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role from definition through tapeout and into first silicon.
Key responsibilities include:
**Hands-on DFT Implementation:** Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features. Integrate DFT IP into internally developed RTL and evaluate third-party IP capabilities. Work directly in RTL, synthesis, and DFT tool flows.
**Pre-Silicon DFT Verification:** Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification. Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
**Physical Design Partnership:** Work closely with backend implementation teams to ensure successful physical realization of the DFT architecture. Guide scan chain partitioning, compression planning, and test clock architecture. Address power-aware test implementation, timing closure considerations, and test mode integration.
**Cross-Functional Execution:** Partner with RTL design, design verification, physical design, package and test engineering, firmware, system software, and silicon validation teams to ensure DFT solutions are correct, compliant, complete, and consistent through silicon bring-up.
**AI-Enabled Engineering:** Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG and coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
**Requirements:**
- BS, MS, or PhD in Electrical Engineering or Computer Engineering
- 8+ years of ASIC development experience
- Extensive hands-on DFT implementation experience on complex SoCs with multiple successful production tapeouts
- Deep understanding of scan architectures and their implementation, including ATPG, memory BIST (including repair), boundary scan, IJTAG, EDT, various fault models, and structural coverage analysis
- Hands-on experience with Siemens Tessent DFT solutions (SSN, EDT, MBIST, RTLpro, Scanpro, Tessent Diagnosis) is required
- Strong RTL design skills using Verilog/SystemVerilog
- Practical experience with synthesis and gate-level verification
- Strong scripting ability in Python, Tcl, Perl, or similar languages
- Excellent debugging skills across RTL, netlists, and silicon failure analysis
- Demonstrated ability to drive technical execution across cross-functional engineering teams
