SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Velaura is seeking a CAD Back-end Lead to own the design automation framework supporting custom design, physical implementation, and signoff flows across multiple ASIC/SoC programs and advanced process technologies.
You will be responsible for developing, integrating, qualifying, and supporting CAD flows spanning custom design, parasitic extraction, circuit simulation, characterization, physical implementation, timing and power analysis, physical verification, and tapeout. This includes owning the CAD framework architecture, EDA tool integration from vendors like Cadence, Synopsys, Siemens EDA, and Ansys, and establishing production-grade automation, version control, regression infrastructure, and release management practices.
Key responsibilities include:
- Develop and maintain reusable CAD frameworks for custom design, custom layout, and hierarchical physical implementation
- Integrate and qualify foundry PDKs, technology files, standard-cell libraries, memories, IP collateral, and EDA tool configurations
- Establish source-control and release-management practices using Git, GitLab, Perforce, or equivalent platforms
- Build regression infrastructure to validate flow functionality, EDA tool upgrades, PDK updates, and methodology changes before production deployment
- Develop automated quality checks and dashboards covering flow status, runtime, resource usage, failures, and QoR metrics
- Partner with foundries, IP providers, and EDA vendors to resolve technical issues
- Evaluate new EDA technologies based on measurable improvements in quality, turnaround time, scalability, and cost
- Architect and develop agentic AI workflows for EDA flow orchestration, regression monitoring, failure classification, root-cause analysis, and production support
- Establish security, access-control, and validation mechanisms for AI applications in proprietary design environments
- Mentor CAD engineers and establish coding standards, code-review practices, and release processes
- Work with central CAD and Infrastructure teams on compute requirements, job scheduling, storage, and capacity planning
- Support production design teams and resolve time-critical flow issues during major project milestones and tapeout
You will collaborate closely with Custom Circuit Design, Custom Layout, Characterization, Physical Design, STA, Power Integrity, Physical Verification, and CAD Infrastructure teams to translate domain-specific methodologies into qualified, scalable, and reproducible production flows.
REQUIREMENTS:
- Deep understanding of the ASIC development lifecycle, with strong knowledge of custom design, physical implementation, signoff, Physical Verification, and tapeout flows
- Experience developing and supporting CAD flows across multiple successful ASIC or SoC programs
- Experience integrating EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and/or other major EDA vendors
- Familiarity with tools such as Cadence Virtuoso, Innovus, Voltus, and Quantus; Synopsys Fusion Compiler, PrimeTime, StarRC, HSPICE, and PrimeSim; Siemens Calibre; and Ansys RedHawk-SC
- Experience integrating foundry PDKs, technology files, timing libraries, physical libraries, extraction decks, verification rule decks, and third-party IP collateral
- Strong software-development and scripting skills using Python, Tcl, Bash, Perl, or similar languages
- Hands-on experience with version-control and collaboration platforms such as Git, GitLab, Perforce, or equivalent tools
- Experience with branching, tagging, merge requests, code reviews, release baselines, configuration management, and rollback strategies
- Experience with automated regression testing, continuous integration, release management, and reproducible engineering practices
- Hands-on experience using modern AI coding assistants and engineering tools as part of software or CAD flow development
- Experience developing AI- or LLM-based applications or agentic workflows that integrate tools, APIs, engineering data, and knowledge sources
- Ability to validate AI-generated code, analysis, and recommendations before deployment in production semiconductor design flows
- Practical understanding of data security, access control, confidentiality, and IP protection when applying AI to proprietary engineering environments
- Strong understanding of Linux environments, distributed compute, batch scheduling, storage systems, and license-dependent EDA workloads
- Strong debugging and root-cause-analysis skills across EDA tools, scripts, design databases, PDK collateral, and compute environments
- Experience supporting production design teams and resolving time-critical flow issues during major project milestones and tapeout
- Excellent communication skills and the ability to collaborate with global teams
PREFERRED QUALIFICATIONS:
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, Computer Science, or a related discipline
- Experience enabling leading-edge FinFET or Gate-All-Around process technologies
- Experience building QoR dashboards, regression analytics, flow-monitoring systems, or automated failure-triage solutions
- Experience deploying production-quality agentic AI workflows for semiconductor design, EDA automation, regression triage, design-data analysis, or engineering knowledge management
- Experience developing and scaling CAD capabilities in a fast-paced or early-stage semiconductor company
