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OpenAI's Hardware organization is seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate-to-package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation.
You will own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Key responsibilities include developing and optimizing high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces; performing package, interposer, and substrate modeling using 2D/3D electromagnetic solvers; and defining package stack-ups, transmission-line structures, via transitions, and return paths based on SI/PI requirements.
You will develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements, translating them into actionable package layout guidelines. Package-level PDN analysis responsibilities include impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, and decoupling optimization. You will drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, and high-speed I/O placement.
The role requires developing simulation methodologies and automation flows for early architecture exploration, design-space optimization, and repeatable SI/PI sign-off. You will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams throughout the design lifecycle.
Required: 5+ years in signal integrity, power integrity, high-speed interconnect design, PDN design, and package electrical design. Strong fundamentals in SI/PI, transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution. Hands-on experience with EM and SI/PI simulation tools (Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent). Experience with package layout environments such as Cadence APD/SIP. Proven ability developing automated design optimization flows. Strong cross-functional communication skills.
Preferred: Advanced 2.5D/3D packaging experience, silicon or organic interposers, HBM integration, IVR integration, or large-body AI/HPC packages. Early-stage SI/PI feasibility methodologies. Memory architecture and high-speed memory interfaces (HBM, DDR/LPDDR). High-speed laboratory validation using VNA, spectrum analyzers, TDR/TDT, oscilloscopes. Knowledge of package and PCB material properties.
