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Salary: USD 150,000 - 200,000 / annual
Positron AI is building next-generation AI inference accelerators designed for low-latency, high-throughput large language model inference. The company recently raised $875 million at a $5 billion valuation (September 2026) and is bringing its custom ASIC (Asimov) and Titan system to market. The team includes engineers from Groq, Lambda, NVIDIA, Meta, and other industry leaders.
As an ASIC Design Engineer, you will design, implement, and deliver IP blocks and subsystems for Positron's inference ASICs/SoCs. Working under the guidance of senior engineers, you will write and verify SystemVerilog RTL, take ownership of well-scoped blocks, and learn the full front-end flow from microarchitecture through RTL signoff.
Key responsibilities include:
**RTL Design & Implementation:** Implement clean, parameterized SystemVerilog RTL for assigned blocks based on microarchitecture specs. Contribute to microarchitecture documentation and block-level interface definition. Add embedded assertions and follow team guidelines for clocking, resets, and power intent.
**Front-End Flows & Quality:** Run and debug lint, CDC/RDC, and synthesis checks on your blocks. Help with timing analysis and work with physical design on block-level timing fixes. Track and report PPA metrics and propose optimizations.
**Interface & Integration Work:** Support integration of standard interfaces and IP (AMBA AXI, DMA engines, memory controllers). Learn and apply protocol requirements for high-performance interconnects and memory interfaces.
**Methodology & Automation:** Follow established coding guidelines, IP packaging standards, and signoff checklists. Write and maintain scripts (Python/Tcl/Make) that improve design flows and team productivity.
**Cross-Functional Collaboration:** Work with Verification to review test plans and debug failures. Help correlate RTL behavior against architecture and performance models. Participate in bring-up and post-silicon debug activities.
**Learning & Growth:** Take part in design reviews, present your work, and incorporate feedback. Build expertise in microarchitecture tradeoffs through mentorship from senior engineers.
The company emphasizes that while this role is posted at a specific level, they are open to hiring at different levels for the right candidate, and responsibilities will be tailored to the hire's experience.
**Requirements:**
- BS/MS in EE/CE or related field with 0–3 years of ASIC/SoC RTL design experience (internships and relevant graduate research count)
- Solid working knowledge of SystemVerilog/Verilog for synthesizable RTL design
- Understanding of digital design fundamentals: clocking, resets, pipelining, FSMs, FIFOs, and clock domain crossing
- Exposure to front-end tools and flows (simulation, lint, synthesis, or STA) from industry or academic projects
- Familiarity with at least one of: AMBA AXI/AHB/APB, DDR/HBM, PCIe, cache/memory hierarchies, or datapath design
- Scripting ability in Python, Tcl, or similar
- Strong problem-solving skills, eagerness to learn, and clear written and verbal communication
**Preferred Qualifications:**
- Coursework, research, or project experience in computer architecture or AI/ML accelerator design (matrix/vector engines, systolic arrays)
- Experience writing SystemVerilog Assertions (SVA) or exposure to formal verification
- Familiarity with low-power design concepts (clock gating, power gating, UPF)
- Experience with cocotb or UVM testbenches
- Exposure to RISC-V, FPGA prototyping, or tapeout of a chip (including academic tapeouts)
