SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Efficient Computer is seeking a Senior Applications Engineer to serve as the technical bridge between customers and internal engineering teams for silicon IP integration. You'll help customers evaluate, integrate, verify, and physically implement Efficient's energy-efficient processor IP in their SoCs, from RTL simulation through tapeout.
Key responsibilities include:
• Act as the primary technical point of contact for customers integrating silicon IP across the full ASIC/SoC flow—RTL simulation, UVM testbench setup, synthesis, floorplanning, place-and-route, timing closure, and signoff.
• Debug complex integration issues across RTL, testbenches, constraints, and physical implementation; distinguish IP defects from configuration errors and protocol misunderstandings.
• Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral (SDC/UPF templates) to accelerate customer ramp time.
• Deliver onsite and remote technical training on IP architecture, verification methodology, coverage closure, timing models, physical abstracts, and implementation best practices.
• Partner with engineering and product leadership to aggregate field evidence, prioritize corrective work, and shape future IP capabilities and deliverables.
• Support pre-sales technical evaluations, helping prospective customers assess IP quality, verification collateral, PPA, floorplan compatibility, and integration effort.
• Lead architecture-to-signoff reviews of customer integrations, identify implementation risks, and recommend corrective actions across configuration, verification, performance, timing, power, and area.
• Exercise upcoming IP releases in representative integration flows; document gaps and work with engineering to close them before external delivery.
• Advise customers on interface/protocol integration, multi-voltage design, power-domain design, DFT stitching, and node-specific signoff requirements.
• Convert recurring support cases into reusable enablement—reference examples, diagnostic playbooks, automation, and self-service guidance.
• Track and report field issues and integration patterns to inform the IP roadmap and process-node support priorities.
Required qualifications: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field. 5+ years in ASIC/SoC verification, physical design, silicon IP integration, or related applications engineering. Strong scripting skills (Python, TCL, Make, shell). Hands-on experience integrating third-party or licensed silicon IP (soft/hard macros, protocol IP, interconnect, standard-cell libraries, memory compilers). Ability to diagnose complex integration issues and communicate findings clearly. Familiarity with multiple foundries and process nodes. One or more of: SystemVerilog/UVM expertise with RTL debugging and coverage-driven verification (Xcelium, VCS, Questa); synthesis, floorplanning, place-and-route, and static timing analysis (Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus); timing models, physical abstracts (Liberty/ECSM/CCS/LEF), constraints, low-power intent (SDC/UPF), and signoff flows (STA, IR/EM, DRC/LVS). Willingness to travel 20–30% for customer site visits.
Nice-to-have: IP vendor applications engineering experience, verification or physical-design consulting background, silicon IP integration at systems/SoC companies, formal verification, protocol compliance suites, verification IP, low-power design, or SoC-level DFT experience.
