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Lumilens is building photonics infrastructure for AI supercomputing, including chip-to-chip optical interconnects and scalable photonic engines. The company is Series B-funded and led by industry veterans.
As Analog Layout Lead, you will drive full-custom analog and mixed-signal layout for next-generation silicon platforms. You'll lead complex physical implementation across advanced CMOS nodes, working closely with circuit design and physical design teams to establish layout methodologies that ensure performance, reliability, manufacturability, and tape-out readiness.
Key responsibilities include:
- Leading full-custom layout of complex analog and mixed-signal blocks (PLLs, ADCs, DACs, LDOs, bandgaps, high-speed I/O) for custom silicon platforms
- Defining and enforcing analog layout methodologies, design rules, and best practices across the physical design team
- Driving parasitic-aware layout strategies to meet noise, matching, signal integrity, and power requirements
- Collaborating with circuit designers to translate schematic intent into optimized physical implementations
- Owning physical verification closure (DRC, LVS, antenna checks, sign-off readiness) across advanced process nodes
- Establishing floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts
- Providing technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency
- Partnering with process technology and design kit teams to evaluate new process nodes and resolve layout-induced performance issues
- Owning long-term physical design roadmaps and methodology investments across multiple silicon programs
Required qualifications: Bachelor's in Electrical Engineering or equivalent; 8+ years of full-custom analog and mixed-signal layout for production silicon in advanced CMOS (preferably 28nm or below); 8+ years hands-on experience with Cadence Virtuoso; experience leading high-performance analog blocks through tape-out; expertise in layout methodologies for matching, shielding, and noise isolation; experience managing and mentoring layout engineers.
Preferred: post-layout simulation flows (Spectre, Calibre), process design kit evaluation, analog layout for photonics/AI/consumer applications, 3D stacking or advanced packaging experience.
