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OLIX is building the next generation of AI computing infrastructure, architecting specialized accelerators (DX-1) for decode workloads using optics and high-speed interconnect. The company is addressing a critical infrastructure gap in AI—chips and power systems cannot scale fast enough to meet demand—and believes a new hardware paradigm will be the defining economic opportunity of the next decade.
As a Senior Mixed-Signal Verification Engineer, you will own verification of analog and mixed-signal subsystems across high-speed IO chains, including CDRs, phase interpolators, clock generation, equalization (DFE/CTLE), samplers, slicers, deserializers, and their digital control loops. This is a high-leverage role at the boundary where analog behavior meets digital control.
Key responsibilities include:
- Owning the verification strategy and test plan from block level through subsystem and top-level integration
- Defining modeling approach and fidelity tiers (real-number models, Verilog-AMS, transistor-level co-sim) with documented trade-offs
- Developing and validating analog behavioral models against transistor-level references
- Building self-checking testbenches and reusable verification components for analog/digital interactions
- Driving AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and owning setup, performance, and runtime optimization
- Defining functional coverage and assertions targeting analog corner behavior (saturation, overflow, loop stability, settling)
- Debugging failures across the analog/digital boundary and driving root-cause analysis to closure
- Partnering with analog and DSP designers to translate intent into checkable models and tests
- Owning block and subsystem verification sign-off for tape-out, including coverage closure
- Building regression infrastructure and flow automation
- Contributing to silicon bring-up and lab correlation
Required qualifications: BS/MS in Electrical Engineering or related field with 5+ years of analog/mixed-signal verification on complex SoCs or mixed-signal IP. Hands-on expertise with Verilog-AMS, real-number modeling, analog-digital co-simulation flows (Spectre AMS, FastSpice), SystemVerilog, assertion-based verification, and analog schematic reading. Strong debug skills across analog/digital boundaries and structured test planning.
Nice-to-have: High-speed SerDes/wireline architecture knowledge (CDR, equalization, PLLs, clocking), calibration/adaptation loop verification experience, UVM expertise, scripting (Python, TCL, Make), mixed-signal IP sign-off through tape-out, and silicon bring-up correlation.
Compensation includes competitive salary commensurate with experience, meaningful stock options, an annual living-local bonus for residents within 20 minutes of the office, and employer-contributed retirement plans.
