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Etched is building custom hardware for frontier AI inference, co-designing chips, racks, software, and manufacturing to optimize throughput and latency. As a Signal & Power Integrity (SI/PI) Engineer, you will own the electrical performance of our AI accelerator platform across silicon, package, and board levels.
You will drive SI/PI analysis and optimization within advanced 2D/2.5D/3D packages, working closely with silicon design, package layout, ASIC physical design, IP, and board teams. Key responsibilities include:
- Conduct SI/PI analysis and optimization across package hierarchies, with focus on high-speed routing (112G/224G SerDes, HBM, D2D interfaces).
- Drive signal integrity requirements into interposer and substrate layout from preliminary design through tape-out.
- Own power delivery network (PDN) design and decoupling strategy, including DC IR drop, dynamic IR drop, and impedance targets across all power rails.
- Manage ball map, C4 bump, and BGA pin assignment in partnership with package layout and board teams.
- Support board-level SI/PI studies and rack-level topology analysis, including test vehicle design and cable characterization.
- Participate in cross-functional design reviews and present risk, sign-off status, and trade-offs to leadership.
You bring 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms. You have proven expertise defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis. You are hands-on with tools like ANSYS HFSS/SIwave, Cadence Sigrity, or Keysight ADS. You have deep experience with advanced packaging technologies like CoWoS, including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs. You have a track record of designing and correlating SI/PI test vehicles against silicon measurements during bring-up and lab characterization.
Nice-to-have skills include familiarity with RTL-to-GDSII context, multi-die/2.5D/3D packaging signoff, chip-package-system co-design, project management across internal teams and external partners, knowledge of ML/LLM/accelerator architectures, and startup experience.
Etched is a fully in-person team in San Jose (Santana Row), betting early on transformer architectures and inference workloads. The company values engineering skills and expects technical staff to contribute across disciplines.
