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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Staff Engineer for Post-Silicon Validation to lead bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, requiring hands-on lab experience and deep understanding of SoC architectures.
You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams. Key responsibilities include:
- Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans
- Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces
- Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation
- Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions
This is a hybrid role based in Austin, TX or Santa Clara, CA. You will gain deep hands-on exposure to cutting-edge RISC-V SoCs, AI accelerators, and high-performance compute platforms, with end-to-end ownership across the silicon lifecycle and opportunities to influence architecture and validation strategy in a highly visible role.
REQUIREMENTS:
- 5+ years of experience in SoC bring-up, validation, and silicon debug
- Strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems
- Comfortable debugging complex hardware/software interaction issues using lab tools and low-level software
- Ability to thrive in cross-functional environments and work closely with RTL, firmware, and software teams
