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Ambiq is a semiconductor company on a mission to enable intelligence everywhere by powering the AI edge revolution with ultra-low-power chip solutions. Built on proprietary sub- and near-threshold technology, Ambiq's chips deliver significant energy efficiency improvements without costly process scaling. Since 2010, the company has shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
As Staff Engineer, Analog Layout, you will drive the physical implementation of key analog subsystems including power management units (PMUs), clocking circuits, and data converters. Your work translates circuit architecture into silicon-ready layout that meets performance, area, matching, and reliability targets. You will work closely with Analog Design and RTL/Physical Design teams to implement custom analog layouts in leading-edge technologies such as 22nm, 12nm, and beyond.
Key responsibilities include:
- Partner with analog designers on chip-level and block-level floorplanning and layout strategy
- Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs
- Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures
- Lead layout for complex blocks and supervise or review layout work from other layout engineers
- Conduct layout design reviews and resolve action items
- Attend circuit design reviews to provide layout feasibility input and guidance
- Work with analog and digital designers to ensure layout meets circuit intent and interface requirements
- Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration
- Support prototype chip bring-up and testing to validate analog circuit blocks against layout-dependent effects
- Support development of manufacturing test plans where layout impacts testability
- Support Product Engineering to meet manufacturing and production needs related to layout and yield
- Support Applications Engineering on layout-related customer questions regarding matching, noise, and reliability
This role requires a well-rounded engineer who has been through multiple design cycles with layout experience across the full flow: from floorplanning and whiteboarding with designers, to detailed layout and parasitic extraction, to LVS/DRC closure and tape-out, through validation and production test support. The position is onsite with an expectation of 5 days per week on-site presence.
Requirements:
- Extensive experience in analog IC layout across full design flow (floorplanning through tape-out and production support)
- Proficiency in transistor-level analog layout with expertise in matching, shielding, and parasitic-sensitive structures
- Experience with leading-edge process nodes (22nm, 12nm, or beyond)
- Strong understanding of parasitic extraction, LVS, DRC, antenna, and fill closure
- Experience with layout design reviews and design rule compliance
- Ability to work collaboratively with analog designers, digital designers, and other layout engineers
- Experience supporting chip bring-up, testing, and manufacturing/production validation
- Self-motivated, creative problem-solver with ability to tackle complex technical challenges
