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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for advanced CPU and AI compute platforms. This is a hybrid role based in Boston, Toronto, Ottawa, or Santa Clara.
In this role, you will lead the development and execution of comprehensive design verification (DV) strategies for CPU and AI accelerator blocks and chiplets, ensuring robust coverage and sign-off. You will build and maintain advanced simulation environments using SV-UVM, C/DPI, Cocotb, and other methodologies to verify complex designs. You will drive test plan ownership across multi-block CPU subsystems, including coverage analysis, regression management, triage, and closure. Collaboration is key—you will work closely with design, architecture, post-silicon, and software teams to review plans and debug issues.
As a senior technical leader, you will mentor junior design verification engineers, sharing expertise in verification flows and AI-assisted tools. You will support emulation and multi-chip verification flows where applicable, optimizing for scalability and efficiency. This role offers the opportunity to learn how large-scale AI SoCs are architected, integrated, and brought to silicon, and how verification choices directly impact design performance, power, and overall silicon success. You will also gain experience building and scaling DV flows supporting cutting-edge compute architectures and integrating cross-functional workflows across design, DV, physical, and firmware teams.
Tenstorrent is a leader in cutting-edge AI technology, having developed a high-performance RISC-V CPU from scratch. The company values collaboration, curiosity, and a commitment to solving hard problems.
REQUIREMENTS:
- Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols (multi-chip and emulation experience a plus)
- Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb
- Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure
- Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams
- Proficient in leveraging modern AI tools (Copilot, Cursor, Claude, Gemini, ChatGPT) to optimize verification workflows
