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Lumilens builds optical interconnect for AI data centers: silicon photonics, mixed-signal ICs, electrical-optical interposers, and systems integration. The company's silicon is shipping in production AI clusters today with rapidly climbing volume.
You will own layout for electronic ICs (EICs) and photonic ICs (PICs)—high-speed analog blocks where layout is the design itself. A parasitic you miss, an uncontrolled return path, or an unchecked current density will cost the part its margin. You will also support photonic IC layout as needed and own the integration of electronic and photonic dies as they come together.
Singapore positions you close to the assembly and test supply chain the company depends on, with design teams across the US, India, and Singapore. You will be the senior layout voice on the ground.
Key Responsibilities:
Block and top-level layout: Own floorplan and layout for high-speed analog and mixed-signal blocks (TIAs, drivers, SerDes front ends, PLL and clocking, references and bias). Execute device-level matching and symmetry using common-centroid, dummies, shielding, guard rings, and substrate isolation. Route high-speed signal paths with control over impedance, coupling, and return paths. Lay out passive and electromagnetic structures (inductors, transformers, transmission lines) and work with designers through EM simulation. Own chip finishing: pad ring, bump and pillar maps, seal ring, density fill, and top-level assembly through tape out.
Physical closure: Drive parasitic-aware layout by iterating with designers on extraction results. Own electromigration and IR drop closure—current density, power grid construction, and analysis that proves it holds at temperature and lifetime. Take blocks through DRC, LVS, antenna, DFM, and ESD and latch-up checks to sign-off.
Photonics and integration: Support PIC layout as needed (waveguide and curvilinear structures, design rules). Own layout of photonic blocks: waveguide routing under bend-radius, spacing, and length-matching constraints; modulator (MZM, ring) and photodetector electrode layout co-optimized with RF drive path; grating and edge coupler placement against fiber-attach and packaging constraints. Build and maintain the photonic PCell library and PDK integration in Virtuoso—curvilinear geometry generation, SKILL and Python automation, grid snapping and stream-out, DRC/LVS methodology for custom photonic cells. Own EIC-PIC integration: micro-bump and pillar alignment, interposer interfaces, and co-layout decisions that make the electrical path work across two dies.
Methodology and team: Set layout standards—reusable structures, PDK and tech file evaluation, automation, documentation, and review practice. Mentor junior layout engineers as the Singapore team grows, and represent layout in design reviews with real authority.
Requirements:
- Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
- 8+ years in custom analog, RF, or high-speed mixed-signal IC layout, including multiple tape outs seen through to silicon.
- Expert-level Cadence Virtuoso, including Layout XL and constraint-driven flows.
- Deep parasitic awareness—ability to look at a schematic and spec and know which nets will decide whether the block works.
- Working command of electromigration and IR drop fundamentals: current density limits, power grid design, and sign-off checks.
- Electromagnetics fundamentals for on-chip structures: inductors, transformers, transmission lines, coupling, and shielding.
- Physical verification fluency: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
- Willingness to overlap with US and India hours during tapeout crunch.
Preferred Qualifications:
- SiGe BiCMOS layout experience and passive/isolation practices those processes demand.
- Advanced FinFET CMOS layout at 7nm and below—multi-patterning, coloring, fin and poly grid constraints, and DRC complexity.
- Photonic IC layout exposure: waveguide routing, curvilinear geometry, photonics PDK design rules.
- Hands-on silicon photonics layout on a foundry platform (Si and SiN waveguides), including PCell development in Virtuoso SKILL or Python-based tools (gdsfactory, KLayout, IPKISS).
- Understanding of how layout drives photonic performance—propagation loss, phase error, optical and thermal crosstalk.
- 2.5D and 3D integration, interposers, micro-bump and copper pillar arrays, co-packaged optics assemblies.
- Layout for optical front ends—TIA, modulator driver, or high-speed serial link blocks.
- Experience standing up layout methodology for a product line in its first generation.
- Scripting for layout automation—SKILL, Python, or both.
