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Salary: USD 126,887 - 166,127 / annual
IonQ is the world's leading quantum computing platform and merchant supplier, delivering integrated quantum solutions across computing, networking, sensing, and security. The company achieved 99.99% two-qubit gate fidelity in 2025, setting a world record in quantum computing performance. IonQ serves customers including Amazon Web Services and AstraZeneca, helping them achieve 20x performance results in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.
You will join the Fab Tapeout and Validation Team as a Senior Mask Layout Engineer, owning full-reticle tapeouts for trapped-ion quantum computers. Your responsibilities include conducting Python-based layout for full-reticle tapeouts with commercial foundries, developing and maintaining internal component PCell and automated circuit layout libraries, and interfacing with designers, test engineers, packaging engineers, and foundry teams to define layout rules and component designs. You will implement physical verification checks of layouts including DRC and LVS, develop detailed documentation of tapeouts, lead layout reviews with team members, and work cross-functionally to understand circuit requirements and improve design, layout, and test workflows.
This is a hybrid/onsite role in College Park, Maryland with up to 10% travel. You will work closely with photonic and ion trap design and testing teams to develop new quantum technology enabling scalable quantum computing, memory, and networking.
REQUIREMENTS:
Must-have:
- Bachelor's degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
- Knowledge of semiconductor manufacturing processes and techniques
- Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
- 2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout
Great-to-have:
- M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
- 5+ years experience generating layout files for complex semiconductor flows with custom elements (MEMS, integrated photonics, superconducting circuits)
- Past ownership of full-reticle tapeouts with commercial foundries
- Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
- Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
- Proficiency in physical verification including DRC, LVS, and ERC
- Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
- Excellent verbal and written communication skills
- Meticulous attention to detail and excellent track record of documenting requirements, implementation plans, and tracking progress
- Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment
