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Q-CTRL is the global leader in AI-powered quantum control infrastructure software. The Quantum Sensing Research and Engineering teams work closely together to translate novel quantum sensing research into real-world products and capabilities. This role is part of a highly dynamic team of approximately 30 specialists in theoretical and experimental atomic physics, cold-atom interferometry, navigation modeling, and Bayesian estimation.
You will develop, integrate, optimize and support FPGA firmware for Q-CTRL quantum sensors. Key responsibilities include implementing and maintaining timing-critical digital processing blocks such as filters, decimation and DSP pipelines; building robust startup, calibration, operation and monitoring routines for autonomous sensor operation; and working with research scientists to translate control concepts into reliable, real-time behavior close to the hardware.
Additional responsibilities include integrating FPGA logic with SoC software to enable reliable, time-synchronized high-bandwidth data capture, DMA transfer and storage; establishing and improving simulation and hardware-in-the-loop testing to support continuous integration and confident field deployment; investigating system-level issues across FPGA logic, firmware, electronics, embedded Linux and higher-level software; contributing to architecture decisions that improve reliability and performance in future sensor revisions; and documenting test, validation and operational procedures.
Q-CTRL was founded in 2017 and operates globally with offices in Sydney, Los Angeles, San Francisco, Huntsville, Berlin, and Oxford. In 2024, the company raised US$113 million in Series B funding, the largest aggregate investment for a quantum software company. Six months later, Q-CTRL delivered the first commercial quantum advantage with Ironstone Opal, a field-validated quantum navigation solution for defense and industry.
REQUIREMENTS:
- Strong foundations in digital design and embedded systems
- Familiarity with SystemVerilog for implementing and maintaining FPGA logic
- Experience with Xilinx SoCs and Vivado-based development workflows
- Digital signal processing experience, including practical implementation of filters, decimation or related signal-conditioning pipelines
- Experience with simulation and verification workflows such as cocotb
- Familiarity with CI/CD development processes for testing, validation and deployment
- Systems programming languages experience (C, C++ or Rust) to interface with FPGA data paths, including DMA-based transfer
- Curiosity about complex systems and persistence to understand how hardware, firmware, software and physics interact
- Experience with, or enthusiasm to learn, timing-critical control systems and high-bandwidth data capture or storage
- Familiarity with low-latency and low-level communications such as TCP/IP, SPI, I2C or CAN bus
- Exposure to embedded Linux, customized operating systems or Yocto (useful but not essential)
- Familiarity with GitHub Actions and CI/CD workflows for cloud testing and deployment
- Collaborative approach and ability to work effectively with engineers and research scientists in an evolving technical environment
