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Salary: USD 500,000 - 850,000 / annual
Anthropic is hiring a Research Engineer to advance Claude's ability to design silicon chips. You'll work within the Code RL (Reinforcement Learning) team, leveraging chip design expertise to create RL environments and evaluation frameworks that teach AI models to excel at hardware design tasks.
Key responsibilities:
- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design verification (including formal methods), and physical design optimization
- Address cross-cutting RL challenges such as EDA-tool latency optimization and proxy reward design
- Conduct experiments, shape the team's roadmap, and deliver work into research and production training runs
- Collaborate with researchers and engineers across Anthropic and externally
The role sits at the intersection of cutting-edge AI research and hardware engineering. You'll work on a domain where AI capability gaps are significant and impactful—hardware design is complex, unforgiving, and exactly the kind of challenge Anthropic wants Claude to master. The RL teams have already contributed meaningfully to all Claude models, with notable impacts on autonomy and coding capabilities in recent releases.
Anthropic's RL organization spans multiple focus areas: enabling models to use computers effectively, advancing code generation, pioneering fundamental RL research for LLMs, building scalable RL infrastructure, and enhancing reasoning. You'll collaborate closely with alignment and frontier red teams to ensure systems are both capable and safe, and partner with applied production training teams to bring research innovations into deployed models.
The company operates as a cohesive team focused on large-scale research efforts with emphasis on impact and long-term goals around steerable, trustworthy AI. Communication skills and collaborative mindset are highly valued.
Requirements:
- Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs
- Fluency with industry EDA tools and processes
- Experience taping out chips and going from spec to silicon
- Ability to balance research exploration with engineering implementation
- Passion for AI's potential and commitment to developing safe, beneficial systems
- Bachelor's degree or equivalent combination of education, training, and professional experience in a field relevant to the role
Strong candidates may also have:
- Experience with reinforcement learning, evaluations, or environments
- Built tooling or automation around chip design flows
- Worked on ML accelerators or high-performance compute hardware
- Familiarity with high-level synthesis or architecture simulators
