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Salary: USD 130,000 - 180,000 / annual
Efficient Computer is rethinking computing from the ground up to solve AI's biggest challenges around energy efficiency. The company's Fabric architecture delivers 10–100x improvements in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks. With the Electron E1 processor now shipping in volume and over $97 million in Series B financing recently announced, the company is accelerating customer deployments and scaling its architecture to data center performance.
You will join the newly formed verification team as a Design Verification Engineer, owning functional verification of blocks and subsystems in the company's SoC, including Efficient's proprietary Fabric technology. Working alongside senior DV engineers, RTL designers, and architects, you will build testbenches, close coverage, and identify bugs before silicon production. This role offers the opportunity to grow your skills while having real influence on products and processes as the company transitions from initial product development to market release and scaled volume production.
Key responsibilities include:
- Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification
- Write verification plans from design specifications in collaboration with design and architecture teams
- Write SystemVerilog assertions and functional coverage models, and drive coverage to closure
- Debug simulation failures, working with designers to root-cause and fix issues
- Contribute to regression infrastructure, automation, and dashboards that track verification progress
- Support gate-level simulation and other sign-off activities
Required Qualifications & Experience:
- Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
- 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout
- Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests
- Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level
- Working knowledge of SystemVerilog Assertions
- Ability to independently debug simulation failures using waveforms, logs, and design knowledge
- Proficiency in Python for test automation, log analysis, and regression flows
- Ability to clearly report verification status and issues to the team
Desirable qualifications include C/C++ experience for reference models or DPI-based verification, exposure to formal verification tools (JasperGold or similar), experience building or using AI agentic flows for DV, knowledge of computer architecture or dataflow architectures, and exposure to power-aware verification (UPF).
