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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a mid- to senior-level Physical Design Engineer to contribute to the physical design of high-performance chips for industry-leading AI/ML architectures. You will work on the complete ASIC implementation lifecycle, spanning synthesis through tapeout, partnering with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs.
In this hybrid role based in Austin, TX, Fort Collins, CO, or Santa Clara, CA, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. You will develop flows and run experiments to optimize power, performance, and area, while understanding how architectural, front-end, and RTL decisions influence physical implementation outcomes.
Tenstorrent is a high-performance AI technology company that has developed a high-performance RISC-V CPU from scratch and is building an industry-leading AI platform. The company values collaboration, curiosity, and a commitment to solving hard problems.
Note: The company welcomes candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the posting level.
REQUIREMENTS:
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with strong logic design fundamentals
- Experience with synthesis, place-and-route flows, and physical design tools
- Familiarity with timing analysis, EM/IR analysis, and power analysis
- Ability to contribute across floorplanning, clocking, I/O planning, timing closure, area improvement, and power optimization
- Strong Tcl, Perl, Shell, and/or Python skills
- Knowledge of low-power techniques such as power gating, multi-Vt, and voltage scaling
- Grounded in logic design fundamentals and gate- and transistor-level implementation
