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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Physical Design CPU Methodology Engineer to define and drive implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes. This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA (power, performance, area) outcomes, and scalable methodology adoption across multiple projects and teams.
You will define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, clock tree synthesis, extraction, static timing analysis, signal integrity, electromagnetic/IR analysis, and physical verification. You will explore AI/ML-enabled physical design tooling, begin synthesis and place-and-route of CPU partitions, and develop new program reference methodology flows. You will drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows that improve predictability, turnaround time, and PPA.
You will partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design. You will learn how to apply AI/ML to physical design for hotspot prediction, congestion forecasting, timing-risk classification, ECO prioritization, IR-drop screening, and flow tuning. You will build reliable, explainable, production-ready data infrastructure, including feature collection, validation, and signoff integration. You will evaluate AI-enabled EDA capabilities and determine where data-driven optimization delivers measurable value over conventional heuristics, and scale CPU methodology, automation, and AI/ML deployment across advanced-node programs, foundries, teams, and the broader organization.
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. The company has developed a high-performance RISC-V CPU from scratch and is building an AI platform that unifies innovations in software models, compilers, platforms, networking, and semiconductors.
REQUIREMENTS:
- 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs
- Deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, signal integrity, EM/IR, extraction, and physical verification
- Experience building or owning physical design methodology, automation, or CAD flows
- High proficiency in Tcl, Python, Perl, or similar scripting languages
- Technical leadership capability to influence across teams, mentor engineers, and drive standards across geographically distributed organizations
