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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking an experienced Mixed Signal IC Layout Engineer to execute full-custom physical layout of analog and mixed-signal integrated circuits. This role involves turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes (12nm–2nm nodes).
You will own the layout of high-speed analog/mixed-signal blocks including PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and high-speed I/Os. Responsibilities include developing optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, and integration into the company's D2D PHY. You will apply best-known layout practices to optimize parasitics (R/C), coupling, IR drop, and electromigration while closing DRC, LVS, ERC, DFM, and Antenna checks. You will support post-layout extraction and simulation, and as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL) to improve team-wide quality and productivity.
Tenstorrent is building cutting-edge AI technology with a focus on high-performance RISC-V CPUs and AI platforms. The company values collaboration, curiosity, and solving hard problems. You will gain deep, hands-on experience with cutting-edge FinFET technologies down to 2nm, learn how to integrate high-speed analog/mixed-signal IP into complex D2D PHY designs, master advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments, and help shape layout flows, methodologies, and automation across the broader team.
REQUIREMENTS:
- Experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os)
- Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna)
- Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon
- Strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts
- Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers
- Typically BSEE or equivalent experience with ~10+ years in analog/mixed-signal layout
