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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Design Verification Engineer to verify next-generation high-performance RISC-V CPU cores. You will work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and identify corner cases in modern out-of-order processors. This is a hands-on role where you will own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure.
You will gain deep hands-on experience verifying high-performance, out-of-order RISC-V CPU cores and learn how CPU microarchitecture decisions translate into RTL and how those designs are verified against architectural intent. You will develop expertise in advanced verification techniques for complex processor pipelines and interacting subsystems, work closely with CPU architects and RTL engineers to understand the full design lifecycle from specification through silicon, and build experience with the challenges of verifying next-generation CPUs designed for AI, HPC, and high-performance computing systems.
The role is remote, based out of North America or Spain. Candidates at various experience levels will be assessed during the interview process, and offers will align with the appropriate level.
**Requirements:**
- 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs
- Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage
- Understanding of CPU architecture and/or microarchitecture, ideally including concepts such as pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling
- Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools
- Strong C/C++ or Python skills and the ability to work effectively with RTL designers, architects, and other verification engineers
