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Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. As Memory Architect, you will lead the translation of Normal's revolutionary Thermo In-Memory Computing architecture from theory into silicon, with the goal of delivering 100-1000× improvements in performance for AI inference.
You will report to the Director of Silicon Engineering and partner with scientists, microarchitects, physical design, and analog design engineers. Your responsibilities span multiple critical domains:
**Architecture for Processing-In-Memory**: Define memory requirements and floorplan enabling in-memory compute capability, including novel memory primitives, read/write circuitry, and row/column decoders.
**Internal Bandwidth and Data Movement**: Architect local and global datapaths, segmented buses, and on-die fabrics that move data between memory arrays and logic.
**Power Grid and Reliability**: Own power distribution, power budgets, thermal limits, redundancy, and ECC to extract peak performance without compromising retention or yield.
**PDK and Fab Path**: Manage access to process design kits and design rules, assess architectural modification limits, and drive tapeout planning from shuttle through test-chip content and production silicon.
**Primitive Device Library**: Partner with analog engineers to set requirements for write circuits, drivers, and multiplexers, ensuring design choices drive architectural performance.
**Memory Interfaces**: Define how custom memory products interface with external hosts (SERDES, PCIe, Ethernet, DDR5, LP6, HBM-class), including command-set extensions and controller/timing implications.
**Modeling and Validation**: Oversee development of SPICE, analytical, and cycle-level models for performance, power, and yield; partner with performance and ML engineers to validate workload-level gains.
This role requires a seasoned engineer who understands that radical performance improvements demand radical paradigm shifts in memory technology.
**Requirements:**
- Substantial experience in memory architecture or circuit design at a memory manufacturer or memory-centric compute company
- Deep understanding of memory array physics: 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability
- Hands-on experience with embedded or random access memory technology and PDKs; experience developing memory test chips through tapeout
- Fluency moving between SPICE-level circuit behavior through architecture-level performance and power models
- Strong fundamentals in one or more programming languages (Python, C, C++) for modeling and performance prediction
- Experience with RTL and SystemVerilog to model and optimize dataflow and specify compute block requirements
- Experience with different memory interface types
- Excellent written and spoken communication skills
**Bonus qualifications:**
- Experience with process-in-memory or near-memory compute
- Experience with non-volatile memory technology
- Experience with DRAM technology including eDRAM
- Major publications at ISSCC, VLSI, IEDM, ISCA, or other major conferences
- Existing relationships with semiconductor manufacturers
