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Lumilens builds optical interconnect for AI data centers, combining silicon photonics, mixed-signal ICs, electrical-optical interposers, and systems integration. Their silicon is shipping in production AI clusters today with rapidly climbing volume.
In this role, you will own layout for electronic ICs (EICs) and photonic ICs (PICs)—high-speed analog blocks where layout is the design itself. A single overlooked parasitic, uncontrolled return path, or unchecked current density can cost the part its margin. You will also support photonic IC layout as needed and own the integration of electronic and photonic dies as they come together.
You will be based in Singapore, positioned close to the assembly and test supply chain, working alongside a senior layout engineer and partnering with design teams across the US, India, and Singapore.
Key responsibilities include:
- Own layout for assigned analog and mixed-signal blocks: device placement, matching and symmetry, shielding, guard rings, and routing from floorplan through clean sign-off.
- Execute parasitic-aware layout, build to designer constraints, run extraction, and communicate results back to design teams when layout reveals unexpected behavior.
- Route high-speed signal paths with attention to impedance, coupling, and return paths; lay out passive and electromagnetic structures under senior direction.
- Run and close DRC, LVS, antenna, and density checks; support electromigration and IR drop analysis.
- Support top-level assembly and chip finishing through tape out.
- Support PIC layout including waveguide and curvilinear structures: photonic components, waveguide routing (bends, tapers, couplers, grating and edge couplers), and modulator and photodetector electrodes.
- Run photonics-specific verification: curvilinear DRC against photonics PDK, waveguide connectivity and port checks, LVS on custom photonic cells, and clean GDS stream-out.
- Build scripts and reusable structures to accelerate the layout team.
REQUIREMENTS:
- Diploma, BS, or MS in Electrical or Electronics Engineering, or equivalent hands-on layout experience.
- 1–3 years in custom analog, RF, or mixed-signal IC layout, including at least one tapeout you contributed to through to silicon.
- Solid working experience with Cadence Virtuoso, including Layout XL and constraint-driven flows.
- Parasitic awareness in practice—understand why matched pairs are drawn as they are and which nets deserve extra care.
- Fundamentals in electromigration and IR drop: current density limits, power routing, and verification checks.
- Fundamentals in electromagnetics for on-chip structures: coupling, shielding, and high-speed routing constraints.
- Physical verification experience: Calibre or PVS DRC/LVS, and parasitic extraction with QRC, StarRC, or equivalent.
- Some scripting for layout automation—SKILL, Python, or both.
- Willingness to overlap with US and India hours during tape out crunch.
PREFERRED QUALIFICATIONS:
- SiGe BiCMOS layout experience and passive/isolation practices.
- Advanced FinFET CMOS layout at 7nm and below—multi-patterning, coloring, fin and poly grid constraints.
- Photonic IC layout exposure: waveguide routing, curvilinear geometry, and photonics PDK design rules.
- Experience with parametric photonic cells (PCells) in Virtuoso SKILL or Python-based tools (gdsfactory, KLayout, IPKISS), and curvilinear-to-grid snapping and fracture rules.
- Familiarity with silicon photonics building blocks: Mach-Zehnder and ring modulators, Ge photodetectors, thermal phase shifters, fiber coupling structures.
- Exposure to 2.5D and 3D integration, interposers, micro-bump and copper pillar arrays.
- Layout on optical front ends: TIA, modulator driver, or high-speed serial link blocks.
