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Efficient Computer is developing ultra-low-power general-purpose processors that use 100x less energy than state-of-the-art alternatives, enabling perpetual AI/ML inference on AA batteries for 5-10 years. The company is seeking a Hardware Technical Program Manager to own silicon programs end-to-end from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release.
You will serve as the operational center of the program: building and defending schedules, driving the critical path, surfacing risks early, and facilitating tradeoff conversations before they become schedule slips. Daily collaboration spans architecture, RTL design, design verification/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem.
Key responsibilities include owning the silicon schedule informed by customer requirements and functional leads; driving weekly execution cadence (program reviews, design reviews, tapeout readiness); coordinating handoffs across all design disciplines; managing dependency chains (IP delivery, PDK releases, EDA versions, emulation capacity); running tapeout checklists and signoff matrices (timing, power, IR/EM, DRC/LVS, DFT coverage); working with supply chain on IP acquisition, silicon arrival, ATE readiness, and ECO decisions; surfacing risk early with quantified mitigation options and schedule impact; facilitating PPA/schedule/scope tradeoffs; interfacing with foundry, OSAT, IP, and EDA partners; delivering executive reporting on program status, risks, and decisions; and tracking resource allocation and budgets.
Required: B.S. in Electrical/Computer Engineering, Computer Science, or equivalent (M.S./MBA a plus); 7+ years in semiconductor/hardware engineering or program management with at least 2 full SoC/ASIC programs from concept through tapeout and silicon bring-up; working fluency in chip design flow (RTL, functional verification, DFT, synthesis, PnR, STA, physical signoff, GDSII, post-silicon validation); ability to build and defend bottoms-up schedules with critical path analysis; track record influencing without authority; strong written and verbal communication; hands-on with Jira, Confluence, MS Project/Smartsheet, and EDA tools (Synopsys/Cadence/Siemens).
Desired: prior hands-on engineering experience in design, DV, or physical design; experience on advanced nodes (16/12/7nm or more); familiarity with AI/ML accelerators or novel compute architectures; experience managing emulation/FPGA prototyping and pre-silicon software enablement; exposure to package/board co-design and OSAT coordination.
