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Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry and critical AI infrastructure. The company develops physics-inspired ASICs in partnership with advanced institutions, with offices across New York City, Silicon Valley, London, Copenhagen, and Seoul.
As a Performance Modeling Engineer, you will own the transaction-level model (TLM) of the company's ASICs—the critical bridge between RTL and the broader modeling stack that architects and verification teams depend on. Your core responsibilities include:
• Building and maintaining a cycle-accurate approximate TLM of compute tiles, memory hierarchy, and interconnect using SystemC, C++, or Python. The model must be fast enough to simulate real AI workloads and accurate enough to drive production design decisions.
• Translating TLM and RTL results combined with physical design into calibrated parameters (latency, bandwidth, energy, utilization, occupancy) that enable end-to-end system-level performance prediction on AI workloads.
• Serving as the verification reference model, providing transaction-level scoreboards and performance checks to the DV and RTL teams, ensuring RTL behavior aligns with the TLM and vice versa.
• Planning modeling work against the hardware roadmap and running sensitivity studies on key parameters (buffer sizes, interface widths, scheduling policies, bus configurations) to deliver actionable recommendations to architecture and hardware teams.
You will work closely with architecture, hardware design, and DV teams, using their feedback to refine the end-to-end system. The role emphasizes applying deep performance modeling expertise to an unconventional architecture that computes differently from traditional systems, directly contributing to Normal Computing's goal of achieving 100-1000× improvement in AI inference.
REQUIREMENTS:
• 5+ years of experience in performance modeling at a major semiconductor company
• Demonstrated proficiency in understanding architectures and transforming that into performant modeling code
• Use of various modeling techniques and languages
• Excellent written and spoken communication skills
BONUS QUALIFICATIONS:
• Experience with AI acceleration hardware
• Experience with architecture-level modeling and cost tools (AccelForge, Timeloop/Accelergy, CACTI, McPAT, gem5)
• Experience with DV methodology
• Hands-on use of LLMs or agentic tools in development workflows
• Exposure to analog, mixed-signal, or unconventional compute
• Experience with memory interfaces (LPDDR, HBM, DDR) and other I/O
