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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is seeking a Front End Design Verification Engineer to verify the fetch unit for their next-generation high-performance RISC-V CPU cores. You will work on the logic responsible for instruction fetch, prediction, decode, and dispatch—keeping the processor fed with the right instructions at the right time. You'll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This role offers a direct impact on the performance and correctness of a high-performance out-of-order CPU.
Tenstorrent is a company leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. The team has developed a high-performance RISC-V CPU from scratch and is passionate about building the best AI platform possible.
In this role, you will gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU. You'll learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently. You'll develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes. You'll also learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments, working alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.
The company welcomes candidates at various experience levels and will assess candidates during the interview process for the appropriate level, with offers aligning accordingly.
**Requirements:**
- 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs
- Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development
- Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution
- Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools
- Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams
