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Embedded SW/Firmware Design Engineer

Chaos - Hawthorne, CA, United States - In-office - posted 2026-10-21

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Salary: USD 160,000 - 290,000 / annual

CHAOS Industries, a defense technology company founded in 2022 and backed by $1B in funding from top-tier investors (8VC, Accel, NEA), is seeking an experienced Embedded Firmware/FPGA Design Engineer to join its R&D and product engineering team in Hawthorne, California. The company specializes in advanced sensing and detection solutions powered by Coherent Distributed Networks (CDN™), serving warfighters, commercial air operators, and border protection teams. In this role, you will design and implement complex FPGA designs targeting next-generation radar and sensor products. You will support system integration of FPGA designs with complex software systems, collaborate with cross-functional teams, and provide technical support for deployed FPGA capabilities in the hands of U.S. and international customers. This is a highly collaborative position offering the opportunity to expand your skillset across multiple product families within the defense and sensing domain. Key responsibilities include: - Design and implement complex FPGA designs for next-generation sensor products - Support system integration of FPGA designs with complex software systems - Support deployed FPGA capabilities for U.S. and international customers - Work full-time on-site in Hawthorne, California The role requires U.S. Person status due to access to U.S.-only data systems. CHAOS offers competitive compensation including base salary, generous pre-IPO stock options, relocation assistance, comprehensive health benefits (medical, dental, vision 100% company-paid), 401(k) with 50% match up to 6%, unlimited PTO, free daily lunch, and 'No Meeting Fridays'. **REQUIREMENTS:** Minimum Requirements: - Bachelor's degree or higher in Computer Engineering, Electrical Engineering, Computer Science, or related field - 5+ years of professional experience performing detailed digital RTL design targeting FPGAs - Extensive experience with complete FPGA design lifecycle: RTL design, behavioral simulation, place and route, timing analysis, hardware integration - Extensive experience developing in Verilog and SystemVerilog - Extensive experience with ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream) - Extensive experience with AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale/Ultrascale+, Versal) - Experience with Network Protocols (TCP/UDP/IP) - Experience with Serial Protocols (I2C, JTAG, UART, SPI, CAN) - Experience using Bash and Python for scripting and testing - Experience modifying software drivers and applications to validate FPGA designs - Experience with Agile lifecycle processes including Scrum, Continuous Integration, and Test-Driven Development Methodologies - Ability to work with minimal supervision and collaborate on small teams - U.S. Person status required Preferred Requirements: - Experience designing and implementing highly performant baseband signal processing in FPGA - Experience translating high-level algorithms from Simulink/MATLAB into RTL including FPGA Vendor IP implementations - Experience developing and implementing software drivers (C/C++/Python) to interface with FPGA designs - Experience with FPGA Ethernet IP blocks (1G/10G/40G/100G) - Experience with Software-Defined Radios (SDRs) such as Ettus, NI, or HackRF - Experience with Analog Device Transceivers - Experience in Ground or Airborne Sensors (Radars, EO/IR, EW, etc.) - Experience with Time Synchronization technologies (NTP/PTP) - Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel) - Experience with VHDL - Experience with high-speed, multi-layer digital PCB design - Current or previous DoD security clearance - Experience with GPUs and/or AI engines - Experience with git - Experience with Bitbucket CI, Jenkins, or similar CI/CD flows - Experience with DoD and related System/SW Architectures and messaging standards (OMS, SOSA, Link-16, etc.)

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