SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 160,000 - 230,000 / annual
Delos Data is a venture-backed startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. The company is led by experienced founders and operators with successful track records of building, scaling, and exiting companies.
You will serve as a Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT (Design for Test) logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and collaborating closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon.
Key responsibilities include:
- Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
- Create and execute coverage-driven verification plans aligned with design specifications
- Use EDA DFT tools (e.g., TestMax, Tessent) to create and run pre-silicon test cases for MBIST and scan fabric
- Develop directed test cases for non-vendor-supplied DFT logic to validate functionality and identify corner cases
- Assist in verifying ATPG patterns at SOC level, along with manufacturing reset sequences
- Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis
- Implement and track functional and code coverage, driving verification to closure
- Develop reusable verification components and write SystemVerilog Assertions (SVA)
- Participate in design and verification reviews, providing input on testability and optimization
- Automate regression testing and enhance verification infrastructure using Python and scripting
- Contribute to continuous improvement of verification processes and methodologies
- Support post-silicon test bring-up debug alongside DFT designers
The ideal candidate has deep hands-on experience with SystemVerilog, UVM, and modern verification workflows, and is comfortable driving verification efforts from planning through closure. Knowledge of DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes is essential. Experience with gate-level simulation and tester pattern formats such as STIL is required.
Desired qualifications include experience with change control systems (especially git) and verifying SoC-level designs.
REQUIREMENTS:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of experience in digital design verification, with at least 2 years in DFT verification specifically
- Strong hands-on experience with UVM-based or similar verification methodologies
- Proficiency in SystemVerilog
- Experience in scripting (preferably Python) and automation
- Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
- Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)
- Solid understanding of digital design fundamentals
- Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)
- Strong analytical and problem-solving skills
- Clear written and verbal communication skills for cross-functional collaboration
- High attention to detail and ability to deliver reliable, high-quality verification outcomes
- Ability to work independently and manage tasks to completion
