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Niobium Microsystems is seeking a Senior Design Verification Engineer to join our expanding team. We develop high-performance SoC products for secure collection, processing, and distribution of critical data, serving DoD and commercial customers with solutions requiring lower power, higher efficiency, and proven security. Founded in 2021 as a spinout from a world-class security and computing systems R&D company, our team combines decades of experience in advanced semiconductor design with expertise in advanced cryptography.
You will collaborate with a small, highly skilled in-house engineering team and multiple global teams of contractors and vendors. Your primary responsibilities include developing test plans, writing testbenches and tests, and debugging issues with the RTL team. You will develop and execute comprehensive test plans for RTL designs using SystemVerilog and UVM, create and maintain testbenches, test cases, and test vectors, and contribute to the development of novel verification methodologies and techniques.
You will lead technical projects and mentor junior team members and contractors, work with 3rd party vendors to collaborate on and adhere to verification quality delivery milestones, run simulations to verify designs against specifications, and analyze results to identify and debug design issues. You will implement coverage tracking and metrics and document plans, environments, test cases, and results for a comprehensive record of all verification strategies.
Niobium is headquartered in Dayton, Ohio with remote employees across the US. We offer flexible work location with remote options, competitive salaries scaled based on experience, employer-paid health care, employer contribution to health savings accounts, flexible time off, 401K employer match, and a highly competitive benefits program.
REQUIREMENTS:
- Bachelor's degree in Electrical or Computer Engineering, Computer Science, or related field
- Minimum 8 years of hands-on experience in SoC verification using UVM
- Experience in gate-level simulation setup and process corner failure analysis
- Experience with Cadence verification tools (Xcelium, Simvision, Jasper)
- Experience writing and debugging RTL using SystemVerilog
- Experience analyzing code and functional coverage to improve testing for corner cases
- Programming experience with C, C++, and/or Python/Perl
- Familiarity with digital design concepts and ASIC development flow
- Strong analytical and problem-solving skills
- Ability to multi-task and prioritize in a fast-paced environment
- Ability to work collaboratively across teams and communicate effectively
- Attention to detail and accuracy
- Willingness to learn and develop new skills
PREFERRED SKILLS:
- Experience verifying RISC-V based systems
- Experience verifying high-speed interfaces (PCIe, DDR)
- Experience with version control systems (Git) and CI/CD pipelines
- Experience with emulation or FPGA prototyping
- Experience with formal verification methodologies
- Familiarity with Chisel hardware description language
