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Ambiq is a semiconductor company on a mission to enable intelligence everywhere by powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on proprietary sub- and near-threshold technology, Ambiq's chips deliver multi-fold improvements in energy efficiency. Since 2010, the company has shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore.
As Staff Engineer, Analog Layout, you will drive the physical implementation of key analog subsystems including PMUs, clocking, and data converters, translating circuit architecture into silicon-ready layout that meets performance, area, matching, and reliability targets. You will work closely with Analog Design and RTL/Physical Design teams to implement custom analog layouts in leading-edge technologies such as 22nm, 12nm, and beyond.
Key responsibilities include:
- Partner with analog designers on chip-level and block-level floorplanning and layout strategy
- Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs
- Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures
- Lead layout for complex blocks and closely supervise or review layout work from other layout engineers
- Conduct layout design reviews and resolve action items generated as a result of these reviews
- Attend circuit design reviews to provide layout feasibility input and guidance to designers and other layout engineers
- Work with analog and digital designers to ensure layout meets circuit intent and interface requirements
- Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration
- Support prototype chip bring-up and testing to help validate analog circuit blocks against layout-dependent effects
- Support development of manufacturing test plans where layout impacts testability (e.g., probe access, trim structures)
- Support Product Engineering to meet manufacturing/production needs related to layout and yield
- Support Applications Engineering on layout-related customer questions (e.g., matching, noise, reliability)
This is an onsite role requiring a presence on site 5 days a week. The successful candidate will be a highly motivated team player who is well-rounded, having been through a number of design cycles with layout-related experience across the full flow, from floorplanning and whiteboarding with designers, to detailed layout and parasitic extraction, to LVS/DRC closure and tape-out, through validation and production test support.
Requirements:
- Extensive experience in analog IC layout across multiple design cycles
- Demonstrated expertise in transistor-level layout, matching, shielding, and parasitic-sensitive structures
- Proficiency in parasitic extraction, LVS, DRC, antenna, and fill closure
- Experience with leading-edge process nodes (22nm, 12nm, or beyond)
- Strong understanding of analog circuit design principles and layout-dependent effects
- Experience supervising or reviewing layout work from other engineers
- Ability to work collaboratively with analog and digital design teams
- Experience supporting chip bring-up, testing, and production validation
