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SWIR Vision Systems (part of onsemi, Nasdaq: ON) is seeking a Staff Digital Verification Engineer to lead verification efforts across IP, subsystem, and SoC-level projects. This is a high-impact individual contributor role where you will take ownership of complex digital verification initiatives and work independently with minimal supervision.
You will architect and develop reusable, scalable verification environments using SystemVerilog and UVM methodologies. Key responsibilities include creating constrained-random, directed, and scenario-based test cases; developing comprehensive scoreboards, monitors, protocol checkers, and assertion-based (SVA) verification models; and establishing robust coverage metrics for functional and gate-level sign-off. You will analyze and debug RTL and gate-level simulation failures, validate timing closure, and support functional signoff activities.
A significant part of the role involves executing fault injection simulations to validate functional safety requirements and fault handling mechanisms—critical for onsemi's automotive and industrial focus. You will also analyze, debug, and enhance C/C++ golden reference models to ensure verification accuracy. Collaboration is essential: you will work closely with design, DFT, physical design, and architecture teams to resolve complex issues and accelerate sign-off.
The role emphasizes modern verification practices, including hands-on experience with industry-standard simulators (Xcelium, Questa) and protocol verification (I2C, AHB/APB, MIPI). You are expected to leverage AI-assisted engineering tools (GitHub Copilot, Microsoft Copilot, LLM-based code generation and debug tools) to enhance regression infrastructure and automate verification workflows.
QUALIFICATIONS:
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field
- 6–10 years of hands-on experience in Digital/ASIC/SoC verification
- Strong expertise in SystemVerilog (mandatory) and UVM (mandatory)
- Familiarity with industry-standard simulators: Xcelium and Questa
- Verification experience with protocols such as I2C, AHB/APB, MIPI
- Exposure to Gate-Level Simulation (GLS) required
- Experience with fault injection simulations (strong advantage)
