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Tensordyne is an AI system solution company building high-performance, low-power generative AI inference systems through custom silicon, hardware, and software. The company enables multimodal generative AI inference acceleration at scale for hyperscaler and neocloud data center customers, with headquarters in Sunnyvale, CA and Munich, Germany, plus distributed remote teams across North America and Europe.
In this Staff-level role, you will lead ASIC physical STA (Static Timing Analysis) design and associated engineering workflow development for Tensordyne's multimodal generative AI inference acceleration products. As a senior individual contributor and tech lead (no direct reports initially), you will guide colleagues to improve frontend physical design with respect to STA at both block and full-chip levels within a fast-paced, agile HPC development environment. You will drive optimization, implementation, and timing exploration workflows—including hierarchical STA, timing analysis, and clock analysis—across the full ASIC chip STA flow.
You will work closely with ASIC team members engaged in design and verification to understand and improve their workflows and EDA needs. This is a hands-on role ideal for ASIC physical design STA experts with multidisciplinary engineering backgrounds and a passion for designing, debugging, optimizing, and finding creative EDA solutions to complex technical challenges. Your contributions will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Tensordyne products.
REQUIREMENTS:
- 10+ years of hands-on ASIC engineering experience, including deep knowledge of VLSI/SoC chip physical design workflows
- Proficiency with EDA tools such as Cadence/Synopsys PrimeTime/Tempus, clock methodology, and development of hierarchical constraints
- Strong physical design knowledge for STA analysis and ability to write SDCs for high-speed IP interfaces such as PCIe, SerDes, and other multi-clock domain blocks
- Experience leading and supporting backend design teams with understanding of STA timing issues, clock trees, routing, and timing ECO generation at block and full-chip levels
- Understanding of Genus/Innovus tool usage with respect to STA
- Excellent analytical, written, and verbal interpersonal skills with ability to collaborate productively within a global engineering team operating at startup pace
- Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related technical field
