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Salary: USD 200,000 - 300,000 / annual
Velaura is building custom silicon for Physical and Embodied AI from a blank sheet. This role owns the front-end automation and design flows that carry silicon from RTL entry through a clean handoff into DFT and implementation.
You will be responsible for the complete RTL design and verification automation pipeline, including build systems, lint checks, CDC (Clock Domain Crossing) and formal verification, register generation, and generator-driven flows for interfaces and integration. You'll own the design verification flows spanning testbench build, regression execution, and coverage collection, as well as emulation and FPGA prototyping bring-up. A key part of this role is building and deploying AI-assisted tooling across design and verification workflows in partnership with CAD and Engineering Infrastructure teams.
Success is measured by enabling front-end engineers to accomplish more while maintaining tool reliability throughout the design cycle. You'll manage tool versions, respond quickly to bug fixes and maintenance requests, measure and improve design/verification productivity, and establish proven workflows as standard practice. You'll also partner with DFT and physical design teams on handoff readiness, owning the DFT-side flows that sit in the front end.
This is an opportunity to help build foundational semiconductor technology for robots, autonomous systems, drones, and other intelligent machines. You'll work alongside experienced leaders and architects who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms.
REQUIREMENTS:
- 8+ years in design verification, design, or CAD engineering, including ownership of a flow area
- Strong SystemVerilog and RTL fluency with ability to read and debug design and testbench code
- Hands-on experience building and running simulation and regression flows including testbench compile, coverage collection, and results triage
- Excellent Python skills and track record of building tools that other engineers maintain
- Working knowledge of front-end EDA tools from Synopsys, Cadence, or Siemens
- Working knowledge of Linux administration, distributed compute (LSF or Slurm), and storage/scaling constraints for large regression workloads
- Familiarity with databases and dashboarding tools (e.g., Grafana) for tracking flow health and regression metrics
- Track record of supporting live engineering flows with responsive issue turnaround and strong communication skills
PREFERRED:
- Experience with UVM, cocotb, or Python-based verification environments
- Hands-on experience applying LLMs or agentic systems to engineering workflows
- Experience taking an SoC from RTL bring-up through tapeout
- Experience with emulation and FPGA prototyping platforms (Palladium, Protium, Veloce, HAPS)
- Experience with retrieval augmented generation, fine-tuning, or evaluation frameworks for code models
- Experience at an early-stage semiconductor company
