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Tensordyne is an AI systems company building high-performance, low-power generative AI inference systems through custom silicon, hardware, and software. The company enables multimodal generative AI inference acceleration at scale for hyperscaler and neocloud data center customers, with headquarters in Sunnyvale, CA and Munich, Germany, plus remote team members across North America and Europe.
As a Senior Compiler Engineer, you will be responsible for building the backend compiler that transforms AI workloads into microcode for Tensordyne's inference hardware (Napier and future generations). The compiler is critical to hardware utilization—the difference between 30% and 90%+ efficiency. This is a clean-slate compiler effort targeting an unusual architecture, and you'll work on fundamental compiler components.
Key responsibilities include:
- Contribute to backend compilation end-to-end: lowering, instruction scheduling, register and resource allocation, and microcode generation
- Optimize the memory hierarchy: SRAM residency, HBM traffic, DMA orchestration, layout, rematerialization, and data movement to keep the machine compute-bound
- Develop tiling, fusion, and software-pipelining strategies to close the gap between theoretical and achieved throughput
- Design compiler interfaces that work for both AI agents and engineers: structured IR access, machine-readable diagnostics, searchable tuning spaces, and actionable performance feedback
- Solve problems conventional batch compilers avoid: dynamic shapes, compile latency, KV-cache management, and different optimization objectives (time-to-first-token vs. steady-state throughput)
- Build and continuously calibrate cost models that predict performance on silicon that doesn't yet exist
- Feed compiler learnings back into ISA and microarchitecture requirements for next-generation silicon
The role emphasizes a co-design mindset where compiler, kernels, runtime, ISA, and silicon are treated as one integrated system. You'll cross traditional boundaries whenever performance opportunities exist.
Requirements:
- Production compiler experience in code generation, optimization, or graph mapping with demonstrated shipped work and measurable results
- Experience with MLIR and/or LLVM, with meaningful contributions to an active compiler stack (LLVM, MLIR, TVM, IREE, XLA, Triton, Inductor, or equivalent internal system)
- Strong modern C++ skills and disciplined approach to testing and correctness (Rust experience is a plus)
- Experience targeting custom accelerators or non-standard ISAs; comfort reading microarchitecture specifications and challenging assumptions
- Strong performance intuition: memory hierarchy, data movement, parallelism, synchronization, occupancy, and factors determining whether theoretical throughput becomes real throughput
- Co-design mindset treating compiler, kernels, runtime, ISA, and silicon as one system
Standing out qualifications:
- Defensible opinions about what today's ML compilers get wrong, backed by evidence
- Work on autotuning, auto-scheduling, or polyhedral compilation
- Hands-on experience using agents in compiler, kernel-generation, or optimization loops
- CUDA/Triton expertise, particularly with CUTLASS or NCCL ecosystems
- Experience with VLIW, systolic, dataflow, or other unconventional architectures
- Open-source compiler contributions available for review
