SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
OpenAI's Hardware organization is seeking a SoC Engineer to architect, design, and integrate custom silicon and systems for advanced AI workloads. This role combines architectural judgment with hands-on implementation across the full development lifecycle, from subsystem requirements definition through pre-silicon validation, silicon bring-up, and post-silicon debug.
You will define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCIe, Ethernet, and die-to-die interfaces. Key responsibilities include developing microarchitecture and RTL design of I/O and SoC subsystems; integrating Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP; designing reset and boot architectures in collaboration with firmware and software teams; incorporating debug, test, and security requirements into the SoC; driving PCIe and high-speed I/O integration including SerDes and die-to-die connectivity; and contributing to power management and security architecture.
You will work directly with third-party IP vendors to define technical requirements, evaluate capabilities, and resolve integration issues. Cross-functional collaboration with architecture, design, verification, physical design, and software teams is essential. You'll also build and apply automation and AI-assisted tools to accelerate design, integration, consistency checking, and debugging while maintaining engineering quality.
The team is small and dynamic, valuing technical breadth, hands-on engineering, and creative problem-solving. You should enjoy stretching across multiple domains, learning unfamiliar system components, and taking broad ownership in an environment where priorities evolve.
REQUIREMENTS:
- Hands-on experience in SoC architecture, RTL design, and subsystem or full-chip integration through implementation and silicon bring-up
- Familiarity with Arm processor subsystems (Cortex-M and Cortex-A) and AMBA protocols/interconnects (AXI, APB)
- Experience with PCIe protocol configuration, controller IP integration, and debugging
- Experience integrating high-speed I/O including SerDes/PHY interfaces and die-to-die links
- Direct experience working with third-party IP vendors on technical evaluation, requirements communication, and integration/debug resolution
- Understanding of reset and boot architecture and hardware-firmware-software interactions during initialization and recovery
- Experience designing for debug, test, and security with systems-level reasoning
- Proficiency writing and debugging Verilog/SystemVerilog; ability to build scripts and tools for efficient integration
- Comfort stretching across multiple domains and rolling up sleeves for hands-on building and debugging
- Interest in creatively applying automation and AI tools to hardware design and integration
Note: Candidates may need to meet certain legal status requirements to comply with U.S. export control laws and regulations.
