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Salary: USD 180,000 - 260,000 / annual
Delos Data is a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. The company is backed by top-tier VC firms and notable angel investors, led by experienced builders and operators with successful exits.
You will own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4 SerDes IP blocks. This is a hands-on technical role requiring deep expertise in taking SerDes IP macros from integration through bring-up, tuning equalization parameters in real systems, and driving links to stable operation across challenging physical channels.
Key responsibilities:
- Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems
- Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates
- Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links
- Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues
- Collaborate with signal integrity, power integrity, hardware, and firmware teams to correlate real-world channel behavior with transceiver settings
- Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows
- Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows
- Help define best practices for SerDes bring-up, tuning, debug, and validation across the company's hardware platforms
The company operates across a mix of remote and on-site locations in the U.S. and Canada, with headquarters in Silicon Valley. The culture emphasizes trust, integrity, respect, accountability, and meaningful work.
REQUIREMENTS:
- Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces
- Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug
- Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER
- Advanced proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers
- Experience with automated, script-based testing and lab characterization, preferably using Python
- Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions
- Strong collaboration skills and ability to work closely with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment
NICE TO HAVE:
- Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments
- Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols
- Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams
- Exposure to channel modeling, compliance testing, and production validation flows
