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IonQ is the world's leading quantum platform and merchant supplier, delivering integrated quantum solutions across computing, networking, sensing, and security. The company achieved 99.99% two-qubit gate fidelity in 2025, setting a world record in quantum computing performance. IonQ's quantum computing services are available through all major cloud providers, and the company serves customers including Amazon Web Services and AstraZeneca.
You will join the Processor Design team at Oxford Ionics (now part of IonQ) as a Senior QPU Design Engineer. In this role, you will be responsible for integrating all features required to operate quantum computers into complex chips, contributing to the advancement of high-performance quantum processing units. You will work closely with scientists and fabrication engineers to bring new ion-trapping chip designs into production and play a key part in shaping the hardware behind the world's most advanced quantum systems.
Key responsibilities include:
- Guiding chips through the complete design process, from requirements to layout and tape-out
- Laying out complex multi-layer chips, including metal track routing and interfaces with photonics and CMOS
- Collaborating with scientists to discuss their requirements and settle on specifications
- Coordinating with other teams to ensure feasibility and compatibility
- Taking charge of projects independently and owning delivery of the final tape-out
- Turning operational requirements into chip layout to enable new technologies
- Expanding the range of features supported by chips to advance utility-scale quantum computing
The role is based in Oxford, England, with a hybrid arrangement requiring three days per week in the office.
Requirements:
- Experience translating design requirements into features
- Hands-on experience in chip layout
- Ability to work across teams and discuss multiple aspects of chip design
- Understanding of how different chip components influence and constrain one another
- Capability to take on layout work independently
- Ability to drive the design process, solve problems, and take responsibility for delivery
- Experience with scripted generation of layout using GDSFactory in Python or similar tools
- Experience using Cadence for IC layout
- Preferred: experience in ion trap design, photonics design, or IC packaging
