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Quantum Motion is a fast-growing quantum computing startup based in London, developing quantum processors using industrial-grade silicon chips. The company operates state-of-the-art cryogenic facilities in Islington and is backed by world-class investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, and others. The team spans quantum physics, IC design, and software engineering across London, Sydney, San Sebastian, and Maryland.
In this role, you will architect, build, and maintain custom process design kits (PDKs) and physical verification enablements as a critical bridge between foundry technologies, custom cryogenic silicon devices, and the circuit design group. You will create custom PDK components from scratch and enable novel silicon spin-qubit and cryo-CMOS circuit design methodologies. No prior quantum physics background is required.
Key responsibilities include:
- Development of custom PDK elements from scratch, including schematic symbols, Layout SKILL PCells, and custom DRC and LVS decks
- Development, qualification, and maintenance of custom Calibre SVRF rule decks tailored for non-standard layout constraints and cryogenic CMOS considerations
- Integration of tier-1 foundry PDKs into Cadence Virtuoso, creating customized library extensions, layer maps, and device callbacks
- Close collaboration with IC designers and layout engineers to establish best practices for physical verification and layout automation
- Documentation of work for peer review and evaluation of layout and enablement work from team members
The role offers competitive salary, share options, contributory pension, private medical insurance, life assurance, cycle-to-work scheme, flexible working, and a central London location in Islington.
REQUIREMENTS:
Must-have:
- Industry degree in Electronic Engineering, IC Layout, Computer Science, or related physical science/engineering field
- 5+ years of hands-on industry experience in IC PDK development and PDK enablement flow management
- Demonstrated proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization
- Demonstrated proficiency in Siemens Calibre Physical Verification tools and SVRF rule writing (specifically DRC and LVS decks)
- Proven hands-on experience in complex DRC and LVS error debugging within analog/mixed-signal or custom digital layout environments
- Strong analytical and problem-solving skills with high self-management and willingness to engage in peer code and layout reviews
- Excellent verbal and written communication skills for collaboration across multidisciplinary physics and IC engineering teams
Nice-to-have:
- Demonstrated experience with advanced deep-submicron CMOS nodes (40nm, 28nm, or below), including familiarity with layout-dependent effects (LOD, WPE, OSE)
- Expert knowledge of Cadence Virtuoso Design Environment and Cadence SKILL/SKILL++ programming
- Expert knowledge of Siemens Calibre Physical Verification Environment
- Familiarity with MOSFET device modeling integration (e.g., BSIM, Verilog-A) or cryogenic device enablement
- General awareness or curiosity regarding semiconductor quantum dots or silicon spin qubit fundamentals
