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Axiado is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-Package (SiP) solutions. The company is building a Trusted Control/Compute Unit (TCU)—a new class of semiconductor integrating hardware security, real-time platform management, and AI-driven optimization for AI infrastructure.
In this role, you will define and drive high-performance, low-power packaging architectures spanning 2D and RDL-based fan-out (2.5D), chiplet-based designs, and heterogeneous integration. You will lead efforts from early technology path-finding through production ramp, working closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Key responsibilities include:
- Serving as technical authority for IC and SiP packaging across multiple products and programs
- Owning package architecture and technology roadmap aligned with product, cost, and scalability goals
- Leading chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL
- Performing and guiding hands-on package design and physical layout for high-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and multi-gigabit interfaces
- Defining substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes
- Driving SI/PI, thermal, mechanical, and reliability trade-offs at system and package levels
- Leading external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness
- Influencing product roadmap, risk management, and investment decisions through technical insight
- Establishing scalable design methodologies, best practices, and reusable packaging flows
Axiado is a well-funded, fast-growing startup (180+ employees) founded in 2019, headquartered in Silicon Valley. The company has received significant industry recognition, including the 2026 AI in Cybersecurity Innovation Award and multiple cybersecurity excellence awards. All employees hold equity.
Requirements:
- BSEE or MSEE (PhD a plus) in Electrical Engineering or related field
- Minimum 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products
- Deep hands-on expertise in Flip-Chip BGA (FCBGA), System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)
- Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs
- Advanced packaging materials and substrate technologies knowledge
- Design-for-Manufacturing (DFM) and yield optimization expertise
- Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment
- Technical leadership of multiple end-to-end packaging programs from early architecture through high-volume production
- Proven experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5/LPDDR5X, USB 3.x, or 10G interfaces
- Experience defining die-to-die and chiplet-based RDL/bump architecture
- Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp
- Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams
- Clear understanding of cost, yield, schedule, and risk trade-offs at product and portfolio level
- Preferred: Cadence Allegro Package Designer (APD) or equivalent EDA tools
- Preferred: SI/PI expertise including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer
- Preferred: Experience building new packaging methodologies or platforms from scratch
