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Salary: USD 191,000 - 253,000 / annual
Anduril Industries, a defense technology company, is seeking a Senior FPGA Verification Engineer to join the Imaging team in Goleta, California. The Imaging team develops state-of-the-art imaging systems leveraging computer vision, perception, electro-optical, infrared, and sensor data to support U.S. and allied military capabilities.
In this role, you will provide technical leadership for FPGA verification efforts on new product lines. You will work closely with an interdisciplinary technical team to define requirements, complete design and analysis, build prototypes, and mature them through ground and flight testing into production systems.
Key responsibilities include:
- Design and architect verification environments using SystemVerilog, OVM/UVM, VHDL, or Verilog
- Develop comprehensive test plans, test cases, and track code and functional coverage metrics
- Create and execute testbenches for RTL block verification
- Recommend new tools and methodologies to improve the group's ASIC/FPGA verification flow
- Contribute to engineering estimates for new program pursuits
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
This is a hands-on technical role with leadership components, requiring you to mentor team members and drive verification strategy while maintaining deep technical expertise in HDL design and simulation.
REQUIREMENTS:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
- 8+ years of professional experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC environments
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
- Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience with revision control systems (Git, Subversion) for source code management and collaboration
- Eligible to obtain and maintain an active U.S. Secret security clearance
PREFERRED QUALIFICATIONS:
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment; familiarity with DFT, manufacturability, and production test concepts
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, shell)
- Experience with industry-standard ASIC/FPGA simulation and synthesis tools (QuestaSim, Synplify, Quartus, Vivado)
