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Salary: USD 191,000 - 253,000 / annual
Anduril Industries is a defense technology company transforming U.S. and allied military capabilities through advanced technology. The Imaging team develops state-of-the-art imaging systems across hardware and software, leveraging computer vision, perception, electro-optical, infrared, and sensor data to provide warfighters and allies with critical advantages.
As a Senior FPGA Verification Engineer, you will join the Imaging team to help design new product lines. Working closely with an interdisciplinary technical team, you will define designs, conduct analysis, build prototypes, and oversee ground and flight testing to mature prototypes into production systems.
Key responsibilities include:
- Design and architect verification environments using SystemVerilog, OVM/UVM, and related methodologies
- Develop written test plans, test cases, and track code and functional coverage metrics
- Create and execute testbenches for RTL block verification using VHDL or SystemVerilog
- Recommend new tools and practices to improve the group's ASIC/FPGA verification flow
- Contribute to engineering estimates for new program pursuits
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
You will apply chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification. This role offers the opportunity to work on cutting-edge defense technology with a team focused on bringing autonomy, AI, computer vision, and sensor fusion capabilities to military systems.
REQUIREMENTS:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
- 8+ years of professional experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in professional FPGA or ASIC development environments
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
- Experience applying chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience with revision control systems such as Git or Subversion for source code management and collaboration
- Eligible to obtain and maintain an active U.S. Secret security clearance
PREFERRED QUALIFICATIONS:
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment, with familiarity of DFT, manufacturability, and production test concepts
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell)
- Experience with industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado
