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SWIR Vision Systems (part of onsemi, Nasdaq: ON) is seeking a Senior Digital Verification Engineer to join their team in Bengaluru. onsemi is a leader in intelligent power and sensing technologies, driving innovations in automotive electrification, industrial automation, sustainable energy grids, and 5G/cloud infrastructure.
In this role, you will develop and execute comprehensive verification plans for subsystem and SoC-level designs, working independently to create reusable verification environments using System Verilog and UVM. You will design constrained-random, directed, and scenario-based test cases, develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models. Your responsibilities include analyzing and debugging RTL and gate-level simulation failures for timing and functional signoff, as well as analyzing and enhancing C/C++ golden reference models for functional verification.
You will execute and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms. Collaboration is key—you'll work closely with design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities. The role also involves leveraging AI-assisted engineering tools (GitHub Copilot, Microsoft Copilot, LLM-based code generation/debug tools, and AI-driven verification productivity solutions) to enhance regression infrastructure and verification automation.
REQUIREMENTS:
- Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field
- 5-7 years of hands-on experience in Digital/ASIC/SoC Verification
- Strong expertise in System Verilog (Mandatory) and UVM (Mandatory)
- Familiarity with industry-standard simulators such as Xcelium and Questa
- Verification experience with protocols such as I2C, AHB/APB, MIPI
- Gate-Level Simulation (GLS) experience is a plus
