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Quantum Motion Technologies is a fast-growing quantum computing scale-up founded by internationally renowned researchers from UCL and Oxford University. The company is developing quantum processors based on industrial-grade silicon chips with applications in materials modelling, medicine, artificial intelligence, and beyond. The team has been recognized in EE Times' "Top 100 Startups worth watching" and recently closed a Series C funding round of $160 million.
We are seeking a Senior Digital IC Design Engineer to join our world-leading team of quantum engineers, IC engineers, theoreticians, and software engineers. This is a rare opportunity to contribute to the development of scalable quantum computers based on silicon technology in a collaborative, cutting-edge research and development environment.
Key Responsibilities:
- Lead digital IC design for quantum control and readout electronics operating in cryogenic environments
- Design low-power, thermally-constrained digital circuits for sub-4.2 K operation
- Integrate digital logic with precision analog/RF front-ends (ADCs, DACs, LNAs, AWGs) for qubit control and readout
- Develop power-aware designs using IEEE 1801 UPF/CPF methodologies
- Contribute to silicon bring-up, testing, and debug of quantum processor chips
- Collaborate across disciplines with quantum engineers and software teams
- Automate and optimize synthesis, physical design, and verification flows
Requirements:
- Deep expertise in low-power dissipation techniques (clock gating, power gating, dynamic voltage scaling) within stringent thermal budgets of cryogenic cooling systems
- Hands-on experience designing, modeling, or characterizing CMOS circuits at sub-4.2 K temperatures and understanding cryo-specific transistor behavior
- Direct integration experience with precision analog/RF front-ends (ADCs, DACs, LNAs, AWGs) for qubit control and readout
- Familiarity with quantum control interfaces, pulse generation, error correction, or cryogenic spin qubit electronics
- Proficiency in power-aware simulation using IEEE 1801 UPF/CPF, formal LEC, and power signoff tools (Voltus, PrimePower)
- Experience with sub-28nm nodes, with strong preference for FD-SOI or FinFET technologies
- Strong scripting skills (TCL, Python) to automate design flows
- Practical knowledge of DFT insertion (Scan, MBIST) and post-silicon laboratory bring-up, testing, and debug
